Multilayer printed wiring board

ABSTRACT

In a core substrate  30 , a ground through hole  36 E and a power through hole  36 P are disposed in the grid formation, so that electromotive force induced in X direction and Y direction cancel out each other. As a result, even if mutual inductance is reduced and a high frequency IC chip is loaded, electric characteristic and reliability can be improved without generating malfunction or error.

TECHNICAL FIELD

This invention relates to a multilayer printed wiring board and providesa technique related to a multilayer printed wiring board capable ofhaving improved electric characteristics and reliability without causingmalfunction, error or the like even if a high frequency IC chip,particularly an IC chip in a high frequency range of 3 GHz or higher ismounted thereon.

BACKGROUND ART

In forming a buildup type multilayer printed wiring board constitutingan IC chip package, interlayer insulating resin is formed on one of oreach of the surfaces of a core substrate having through holes formedtherein and via holes for interlayer conduction are opened by a laser orphoto etching, whereby an interlayer resin insulating layer is therebyformed. A conductor layer is formed on the via holes by plating or thelike and etching and the like are performed to form a pattern, thuscreating a conductor circuit. Further, by repeatedly forming theinterlayer insulating layer and the conductor layer, the buildupmultilayer printed wiring board is obtained. By forming solder bumps andexternal terminals (PGA/BGA's or the like) on the front layer of theboard at need, the board becomes a substrate capable of mounting an ICchip thereon or a package substrate. The IC chip is C4 (flip-chip)mounted, whereby the IC chip is electrically connected to the substrate.

As prior art of the buildup type multilayer printed wiring board, thereare known JP1994-260756A and JP1994-275959A. In both of thepublications, a land is formed on a core substrate having through holesfilled with resin filler, interlayer insulating layers having via holesformed therein are provided on the both surfaces of the substrate,respectively, a conductor layer is formed by an additive method and theconductor layer is connected to the land, thereby obtaining a highdensity multilayer wiring board having fine wirings formed thereon.

However, as the frequency of an IC chip is higher, the noise ofoccurrence of becomes higher. Particularly if the frequency of the ICchip exceeds 3 GHz, the frequency of occurrence of malfunction or errorconsiderably increases. If the frequency exceeds 5 GHz, the IC chipoften turns inoperative. Due to this, it cannot perform operations thatthe computer should do, i.e., cannot perform desired functions andoperations such as delay of the recognition of an image, the changeoverof a switch and the transmission of data to the outside of the computer.

If the substrate for an IC chip of this type which can not perform theoperations is to be subjected to a non-destructive test and to bedissembled, no problems such as short-circuit or opens do not occur tothe substrate itself and if the IC chip having a low frequency(particularly less than 1 GHz) is mounted on the substrate, then nomalfunction or error occurs to the IC chip.

A high frequency IC chip has enabled high-speed operation whilesuppressing generation of heat by increasing or decreasing consumptionof power intermittently. For example, it consumes electric power ofseveral tens W instantaneously although it usually consumes only severalW. According to an estimation, if loop inductance of a printed wiringboard is high at the time of this consumption of several tens W,supplied voltage drops thereby leading to malfunction.

The present invention intends to propose an IC chip for high frequencyregion, particularly, a multi-layer printed wiring board or a packagedboard in which malfunction or error never occurs even if 3 GHz isexceeded.

DISCLOSURE OF THE INVENTION

As a result of accumulated researches for achieving the above-mentionedobject, the inventor and other people have reached an inventionincluding a following content as its major configuration. That is, thetechnical feature of the present invention exists in a multi-layerprinted wiring board in which an interlayer insulating layer and aconductive layer are formed on both sides or a single side of a coresubstrate having a plurality of through holes and electric connection iscarried out through via holes, the through holes in the core substratebeing disposed so that a ground through hole and a power through holeadjoin each other.

By disposing the ground through hole adjacent to the power through hole,induced electromotive forces cancel out each other because thedirections of the induced electromotive forces are opposite. As aresult, noise is reduced so that the function of a substrate neverdrops. Thus, malfunction and delay are eliminated. In other words,mutual inductance can be reduced. Then, loop inductance of a printedwiring board decreases, so that the voltage of transistor in the ICalways stabilizes thereby operating the transistor normally.

At this time, it is more preferable if a distance between the boththrough holes are shorter. That is, as a result, inductance can bereduced relatively.

A further technical feature of the present invention exists in amulti-layer printed wiring board in which an interlayer insulating layerand a conductive layer are formed on both sides or a single side of acore substrate having a plurality of through holes and electricconnection is carried out through via holes, the through holes in thecore substrate including two or more ground through holes and two ormore power through holes, such that the ground through hole and thepower through hole are disposed in the grid formation or in a staggeredformation at adjacent positions.

In case of the grid formation, ground through holes (or power throughholes) are disposed diagonally and power through holes (or groundthrough holes) are disposed at the other positions. Such a configurationmakes electromotive forces induced in X direction and Y direction cancelout each other.

This will be explained with reference to FIG. 11(A) showingschematically an example in which the through holes are disposed in thegrid formation. As for through holes disposed in the grid formation,power through holes VCC1, VCC2 are disposed at an equal interval to aground through hole GND1 and a ground through hole GND 2 is disposeddiagonally with the ground through hole GND1. Due to this 4-core (quad)structure, cancellation of induced electromotive forces by two or moreground through hole VCCs (or power through hole GNDs) to a single powerthrough holeGND (or ground through hole VCC) is carried out. Thus,because mutual inductance of the through holes can be reduced and aninfluence of induced electromotive force is eliminated, malfunction ordelay becomes unlikely to occur.

This will be explained with reference to FIG. 11(B) showingschematically an example in which the through holes are disposed in thestaggered formation. As for the through holes disposed in the staggeredformation, ground through holes GND1, GND2, GND3, GND4 are disposed atan equal distance around a single power through hole VCC1. At this time,it is preferable to dispose the ground through hole GND and the powerthrough hole VCC with the equal distance. Due to this structure,cancellation of induced electromotive forces by one or more powerthrough holes VCC (or ground through holes GND) to a single groundthrough hole GND (or power through hole VCC) is executed. Thus, becausemutual inductance of the through holes can be reduced and an influenceof induced electromotive force is eliminated, malfunction or delaybecomes unlikely to occur.

The grid formation reduces inductance more than the staggered formation.FIG. 11(A), (B) are schematic diagrams showing a case where a minimumunits of two or more ground through holes and two or more power throughholes are disposed. FIG. 11(D), (E) show a case where four of theminimum units are disposed. FIG. 11(D) shows a case of the gridformation and FIG. 11(E) shows a case of the staggered formation. To aVCC located outside of the grid formation, two GNDs are disposed at thenearest positions. On the other hand, to a VCC located outside of thestaggered formation, a single GND is disposed at the nearest position.To a VCC inside of the grid formation and a VCC inside of the staggeredformation, four GNDs are disposed at the nearest position.

Originally, the ground through holes GND and the power through holes VCCare likely to be affected by magnetic field. Thus, in case of highfrequency, high-speed IC chip, its inductance increases. Consequently,the supply of power to a transistor in the IC is delayed so that thetransistor does not turn ON. A problem as a substrate for operating thehigh-speed driven IC properly is generated. Thus, it is necessary toconsider an arrangement for suppressing an influence of inductance bythe ground through hole GND and the power through hole VCC. For example,a demand for higher density (higher density, fine wiring) is not alwayssatisfied by just disposing the through holes at a narrow interval. Theabove-described arrangement reduce each inductance. Then, the loopinductance is reduced so that the supply of power to the transistor ofthe IC is not delayed.

A distance between the ground through hole and the power through hole (apitch indicated in FIG. 11(C); a distance between the center of theground through hole GND and the center of the power through hole VCC) isdesired to be in a range of 60 to 600 μm. By reducing the distancebetween the walls of the through holes, mutual inductance can bedropped. If it is less than 60 μm, any insulating gap cannot be securedbetween the through holes, thereby causing such a fault asshort-circuit. Due to an insulating gap or the like, it can be difficultto set the loop inductance within the range of a design permissiblevalue. If it exceeds 600 μm, even if the through holes are disposed inthe grid formation or in the staggered formation, the effect of reducingthe loop inductance drops. If it is in the range of 80 to 600 μm,insulating gap can be secured so as to reduce the loop inductance andimprove the electric characteristic.

It is desirable that the diameter of the ground through hole (outsidediameter of the through hole shown in FIG. 11(C)) is 50 to 500 μm andthe diameter of the power through hole is 50 to 500 μm.

If it is less than 50 μm, it is likely to be difficult to form anyconductive layer within the through hole. Additionally, self-inductancerises.

Although if it exceeds 500 μm, the self-inductance per piece can bereduced, the quantity of ground lines and power lines which can bedisposed within a limited area decreases, so that reduction of entireinductance by converting the ground line and the power line intomultiple lines cannot be achieved. The reason is that if through holesare disposed in the grid formation or in the staggered formation, such afault as short-circuit occurs depending on a through hole pitch. Thatis, formation of the through holes itself becomes difficult.

It is more preferable to form through holes in a range of 75 to 585 μm.In this range, the self-inductance can be dropped and by increasing thequantity of wires, entire inductance can be reduced thereby the electriccharacteristic being improved. Further, the through hole pitch can beturned into a narrow pitch.

It is preferable that one or two or more through holes are soconstructed that all layers are stacked from just above the through holeor on land of the through hole up to an outermost layer. They aredesired to be formed just above the through hole. To connect the throughholes, land is formed on the through holes with a lid structure by lidplating and via-on-through holes are formed in a stack conditionthereon. As a result, from the IC chip to an external terminal orcapacitor are placed on a straight line so that they are connected atthe shortest distance thereby reducing the inductance further. In thiscase, the via holes are more preferred to be formed on the GND throughhole and the VCC through hole in the grid formation or in the staggeredformation. All through holes disposed just below the IC in the gridformation or in the staggered formation are preferred to be in the stackcondition and the via holes are preferred to be filled with conductor.

The ground through hole and the power through hole are preferred to bedisposed just below the IC chip.

By disposing them just below the IC chip, a distance between the IC andan external terminal or capacitor can be reduced thereby dropping theinductance. As the core substrate in this case, it is permissible to useresin substrate, ceramic substrate or metal substrate impregnated withcore material such as glass epoxy resin, composite core substrateemploying resin, ceramic and metal compositely, a substrate providedwith a (power) conductive layer in the inner layer of those substratesand multi-layer core substrate in which three or more conductive layersare formed.

It is permissible to use a core substrate formed according to a methodfor a general printed wiring board, for forming a conductive layer on asubstrate in which metal is buried, by plating or sputtering in order toincrease the thickness of the power layer.

In case of the multi-layer substrate, the sum of the thicknesses of anouter layer and inner layer of the core substrate is the thickness ofthe core conductive layer. That is, the purpose of forming intomulti-layer structure is to increase the thickness of the conductivelayer of the core substrate and its effect is not changed.

In this case, the core substrate may be composed of three layers (outerlayer+inner layer). As required, it is permissible to use an electronicpart accommodating core substrate in which such parts as capacitor,dielectric layer and resistor are buried in the inner layer of the coresubstrate. The insulating material of the core is permitted to be ofdielectric material.

The core substrate of the present invention is defined as follows. It isa hard base material impregnated with core material and the like and viahole is formed on both sides or a single side thereof using insulatingresin layer containing no core material by photo via or laser and then,a conductive layer is formed to achieve electric connection betweenlayers. The thickness of the core substrate is relatively larger thanthe thickness of the resin insulating layer. Basically, in the coresubstrate, conductive layers, mainly power layers, are formed andsignals lines are formed only for connecting the front and rearsurfaces.

In this case, the conductor thicknesses of the GND layer and the VCClayer formed in the core substrate are desired to be large.Particularly, it is more preferable that the thickness of the conductivelayer in the core substrate is larger than the thickness of theconductive layer on the interlayer insulating layer.

By increasing the thickness of the conductive layer in the coresubstrate, the conductive layer of the power layer in the core substratethickens so that the strength of the core substrate is intensified. As aresult, even if the core substrate itself is thinned, warpage andgenerated stress can be relaxed in the substrate itself.

Further, the volume of the conductor itself can be increased. Byincreasing the volume, resistance in the conductor can be reduced.Consequently, electric transmission in the signal line is kept frombeing hampered. Thus, no loss is induced in a transmitted signal and thelike. Even thickening only the conductive layer in a core portion exertsthat effect.

By using the conductive layer as the power layer, the capacity of powersupply to the IC chip can be improved. By using the conductive layer asa ground layer, noise overlapping on a signal and power to the IC chipcan be reduced. That is, reduction of resistance of the conductor iskept from hampering the supply of power. For the reason, when the ICchip is mounted on the multi-layer printed wiring board, loop inductancefrom the IC chip to the substrate to power supply can be reduced. As aconsequence, the shortage of power at the time of an initial operationdecreases, thereby making the shortage of power unlikely to occur andthus, even if an IC chip having a higher frequency region is mounted,malfunction or error at the initial startup is never generated.

In case where power is supplied to the IC chip through IC chip tosubstrate to capacitor or power layer to power supply also, the sameeffect is exerted. The above-mentioned loop inductance can be reduced.

Particularly when the thickness of the conductive layer used as powerlayer of the core substrate is larger than the thickness of theconductive layer on the interlayer insulating layer on a single side orboth sides of the core substrate, the above-described effect can beexerted to a maximum extent. The conductive layer on the interlayerinsulating layer in this case means a conductive layer formed by platingor sputtering on the interlayer resin insulating layer formed of resinand impregnated with no core material, in which a via hole is formed asa non-through hole for connecting between layers. In addition to this,if any via hole is formed although it is not limited to any particularone, that conductive layer falls under the above-mentioned conductivelayer.

The power layer of the core substrate may be disposed on the frontsurface or inner layer of the substrate or both of them. The inner layermay be formed into multi-layer structure of two or more. Basically, ifthe power layer in the core substrate is thicker than the conductivelayer on the interlayer insulating layer, that effect is kept. It isdesired to be formed in the inner layer.

Assuming that the thickness of the conductive layer on the coresubstrate is α1 and the thickness of the conductive layer on theinterlayer insulating layer is α2, preferably, α2<α1≦40α2.

If α1≦α2, there is no effect to the power shortage. That is, in otherwords, regarding voltage drop generated at the initial operation, aneffect of suppressing the degree of the drop is not evident.

In the case of α1>40α2, if any conductive layer is formed on the frontsurface side of the core substrate, it is difficult to form a land andthe like for connecting with the core substrate. Further, if aninterlayer insulating layer is formed as an upper layer, unevennessintensifies so that swelling is generated in the interlayer insulatinglayer and thus, it comes that impedance cannot be matched.

The thickness α1 of the conductive layer is more preferred to be 1.2α2≦α1≦20α2. It has been verified that in this range, no malfunction orerror of the IC chip due to the voltage shortage (voltage drop) isgenerated.

It is preferable to use a multi-layer core substrate having three ormore conductive layers.

At this time, preferably, two or more layers of the GND layers or VCClayers are formed and the GND layer and the VCC layer are disposedalternately. The thickness of each insulating layer between respectiveconductive layers is preferred to be substantially equal. The reason isthat because operations of reducing both inductances are executeduniformly, total inductance can be reduced easily. Further, impedance iseasy to match so as to improve the electric characteristic.

What is more preferable is that there are provided two or more VCClayers and GND layers. As a result, the GND layer and the VCC layerdisposed in the inner layer reduces mutual inductance as compared withthe surface portion. The effect appears more conceivably.

A distance between the GND layer and the VCC layer is preferred to be inthe range of 25 to 400 μm. If it is less than 25 μm, it is likelydifficult to secure insulation characteristics regardless of material.If reliability test such as porosity test is carried out, short-circuitcan occur between conductive layers. If it exceeds 400 μm, the effect ofreducing inductance is reduced. That is, because of such a distance, theeffect of mutual inductance is cancelled out.

For both the GND layer and the VCC layer, it is preferable to increasethe thickness of their conductive layers. The reason is that byincreasing both the volumes, the effect of reduction of resistance iseasy to obtain. The thickness of the conductor is preferred to be in therange of 25 to 500 μm. If it is less than 25 μm, the effect of reductionof resistance is likely to weaken. If it exceeds 500 μm, swelling can begenerated in a conductor circuit of a signal line or the like formedabove it, so that a problem occurs in points of impedance matching. Ademand for forming the substrate itself into a thin film becomesdifficult to satisfy because the substrate itself comes to thicken. Inthis case, it is preferred to be larger than the thickness of theconductive layer in the interlayer insulating layer.

Material of the core substrate was verified with a resin substrate andit was verified that the same effect was secured in ceramic substrateand metal core substrate as well. As the material of the conductivelayer, copper was used and it was not verified in case of other metalsthat the effects were cancelled out so that malfunction or errorincreased. Thus, it is considered that a difference of material of thecore substrate or a difference of material for forming the conductivelayer does not influence the effect. What is more preferable is that theconductive layer in the core substrate and the conductive layer in theinterlayer insulating layer are formed of a same metal. Becausecharacteristics such as electric characteristic and thermal expansioncoefficient and physical property are not changed, this effect can beexerted.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a step diagram showing a method for manufacturing a multilayerprinted wiring board according to Embodiment 1 of the present invention.

FIG. 2 is a step diagram showing the method for manufacturing themultilayer printed wiring board according to Embodiment 1.

FIG. 3 is a step diagram showing the method for manufacturing themultilayer printed wiring board according to Embodiment 1.

FIG. 4 is a step diagram showing the method for manufacturing themultilayer printed wiring board according to Embodiment 1.

FIG. 5 is a step diagram showing the method for manufacturing themultilayer printed wiring board according to Embodiment 1.

FIG. 6 is a step diagram showing the method for manufacturing themultilayer printed wiring board according to Embodiment 1.

FIG. 7 is a step diagram showing the method for manufacturing themultilayer printed wiring board according to Embodiment 1.

FIG. 8 is a cross-sectional view for the multilayer printed wiring boardaccording to Embodiment 1.

FIG. 9 is a cross-sectional view showing a state in which an IC chip ismounted on the multilayer printed wiring board according to Embodiment1.

FIG. 10(A) is a X-X cross-sectional view of the multilayer printedwiring board shown in FIG. 8, FIG. 10(B) is a cross-sectional view for amultilayer printed wiring board according to modified example ofEmbodiment 1.

FIG. 11(A) is an enlarged explanatory view showing inside dotted line Iin FIG. 10(A), FIG. 11(B) is an enlarged explanatory view showing insidedotted line II in FIG. 11(B), FIG. 11(C) is an explanatory view showingpitch of through holes, FIG. 11(D) is an explanatory view showing ploverarrangement, and FIG. 11(E) is an explanatory view showing latticearrangement.

FIG. 12 is a cross-sectional view for the multilayer printed wiringboard according to modified example of Embodiment 1.

FIG. 13 is a cross-sectional view for the multilayer printed wiringboard according to Embodiment 2.

FIG. 14 is a cross-sectional view for the multilayer printed wiringboard according to modified example of Embodiment 2.

FIG. 15 is a cross-sectional view for the multilayer printed wiringboard according to Embodiment 3.

FIG. 16 is a table showing a measured result of the loop inductance asto the lattice arrangement, the plover arrangement and randomarrangement of through holes.

FIG. 17(A) is a table showing a result of insulation layer crack testand conductive test as to the lattice arrangement, the ploverarrangement and random arrangement of through holes, FIG. 17(B) issimulated result of the loop inductance as to the lattice arrangement,the plover arrangement and random arrangement of through holes.

FIG. 18 is a graph showing a measured result of the loop inductance asto the lattice arrangement, the plover arrangement and randomarrangement of through holes.

FIG. 19 is a graph showing a maximum voltage drop quantity (V) for (aratio of sum thickness of each conductive layers of multilayercore/thickness of conductive layer on interlayer insulating layer).

BEST MODE FOR CARRYING OUT THE INVENTION

The multi-layer printed wiring board according to a first embodiment ofthe present invention will be described with reference to FIGS. 1-9.

First Embodiment 4-Layer Multi-Layer Core Substrate

First, the configuration of a multi-layer printed wiring board 10according to the first embodiment will be described with reference toFIGS. 8, 9. FIG. 8 shows a sectional view of the multi-layer printedwiring board 10 and FIG. 9 shows a condition in which an IC chip 90 ismounted on the multi-layer printed wiring board 10 shown in FIG. 8, andthis is mounted on a daughter board 94. As shown in FIG. 8, themulti-layer printed wiring board 10 utilizes a multi-layer coresubstrate 30. A conductor circuit 34 and a conductive layer 34P areformed on the front side of the multi-layer core substrate and theconductor circuit 34 and a conductive layer 34E are formed on the rearside thereof. The conductive layer 34P on the upper side is formed as aplain layer for power supply and the conductive layer 34E on the lowerside is formed as a plain layer for grounding. A conductive layer 16E isformed as an inner layer on the front side inside the multi-layer coresubstrate 30 and a conductive layer 16P is formed on the rear side. Theconductive layer 16E on the upper side is formed as a plain layer forgrounding and the conductive layer 16P on the lower side is formed as aplain layer for power supply. Connection of the plain layers 34P, 16Pfor power supply is carried out by the through hole 36P for power supplyand the via hole. Connection of the plain layers 34E, 16E for groundingis carried out by the through hole 36E for grounding and the via holes.Connection of signals on the upper side and lower side of themulti-layer core substrate 30 is carried out through the signal throughhole 36S and via hole. The plain layer may be a single layer provided ona single side or composed of two or more layers. It is preferable thatit is formed of two to four layers. Because improvement of the electriccharacteristic in a case of four or more layers has not been verified,forming multiple layers more than four only provides the same effect asthe four layers. Particularly, the reason why the inner layer iscomposed of two layers is that the degrees of elongation of thesubstrates are arranged neatly in terms of stiffness matching of themulti-layer core substrate, so that warpage is unlikely to occur. Ametallic plate 12 which is electrically isolated may be accommodated inthe center of the multi-layer core substrate 30 (Although the metallicplate 12 takes a role as a core material, it is not electricallyconnected to the through hole or via hole. Mainly, this serves forimproving the stiffness against the warpage of the substrate. Further,if a low thermal expansion metal such as 36 alloy and 42 alloy is usedas the metallic plate, the thermal expansion coefficient of a printedwiring board can be reduced. This makes the IC and bump difficult todestroy.) On the front surface side of the metallic plate 12 is formedthe conductive layer 16E as an inner layer via the insulating resinlayer 14 and on the rear surface side is formed the conductive layer16P. Further, the conductor circuit 34 and the conductive layer 34P areformed on the front surface side via the insulating resin layer 18 andthe conductor circuit 34 and the conductive layer 34E are formed on therear surface side. According to this embodiment, the thickness of eachconductive layer in the inner layer of the multi-layer core substrate is70 μm and the thickness of the conductive layer on the front and rearsurface sides is 15 μm.

On the conductive layers 34P, 34E on the surface of the multi-layer coresubstrate 30 are disposed interlayer resin insulating layer 50 in whichthe via hole 60 and the conductor circuit 58 (12 μm) are formed andinterlayer resin insulating layer 150 in which the via hole 160 andconductor circuit 158 (12 μm) are formed. Solder resist layer 70 isformed above the via hole 160 and the conductor circuit 158. Bumps 76U,76D are formed in the via hole 160 and the conductor circuit 158 via anopening portion 71 in the solder resist layer 70.

As shown in FIG. 9, the bump 76U on the upper side of the multi-layerprinted wiring board 10 is connected to a signal land 92S, a power land92P and a ground land 92E of the IC chip 90. Further, a chip capacitor98 is mounted. On the other hand, the external terminal 76D on the lowerside is connected to a signal land 96S, a power land 96P and a groundland 96E on the daughter board 94. The external terminal in this caserefers to PGA, BGA, solder bump and the like.

FIG. 10 shows a sectional view taken along the line X-X of themulti-layer printed wiring board 10 of FIG. 8. That is, FIG. 10 shows aplan view of the core of the multi-layer core substrate 30. In theFigures, for convenience of understanding, the power through holes 36Pare marked with a downward symbol (+ in the Figure) and the groundthrough holes 36E are marked with a upward symbol (black circle in thecenter of a hole) and the signal through holes 36S are marked withnothing. FIG. 11(A) is an explanatory diagram showing a portion Iindicated with dotted line in FIG. 10(A) in enlargement. According tothe first embodiment, the power through hole 36P and the ground throughhole 36E are disposed in the grid formation at adjacent positions. Thatis, ground (or power) through holes are disposed at diagonal positionsand power (or ground) through holes are disposed at the other positions.Such a configuration cancels out electromotive forces inducted in the Xdirection and Y direction.

As for the through holes disposed in the grid formation as describedabove with reference to FIG. 11(A), a pair of the ground through hole36E (GND1) and the power through hole 36P are disposed at an equalinterval in the grid formation and the ground through hole 36E (GND2) isdisposed diagonally with the GND1. Due to this 4-core (quad) structure,cancellation of induced electromotive forces by two or more VCCs (orGNDs) to a single GND (or VCC) is carried out. Thus, because mutualinductance can be reduced and an influence of induced electromotiveforce is eliminated, an influence of noise can be reduced and further bydecreasing the amount of inductance, loop inductance drops so that novoltage drop occurs in an IC chip in which consumption of power changesintermittently when the consumption of power increases, thereby makingmalfunction and delay difficult to occur.

Further, as shown in FIG. 8, the power through hole 36P and groundthrough hole 36E disposed in the center of the multi-layer coresubstrate 30 adopt such a stack structure in which the via hole 60 andthe via hole 160 are provided just above the through hole. To connectthe through holes 36E, 36P with the via hole 60, a land 25 having a lidstructure is formed of lid plating over the through hole 36E and thethrough hole 36P and the via hole 60 is formed thereon in a stackcondition. Further, the via hole 160 is provided just above the via hole60 on the upper side, so that the via hole 160 is connected to the powerland 92E and ground land 92E of the IC chip 90 via the bump 76U.Likewise, the via hole 160 is provided just below the via hole 60 on thelower side and the via hole 160 is connected to the power land 96P andground land 96E of the daughter board 94 via the bump 76D.

Because of the via-on-through hole and stack structure, from the IC chip90 up to the bumps (external terminals) 76E, 76P of the daughter boardor a capacity (not shown) comes on a same straight line so as to providea shortest distance, thereby reducing inductance further. The powerthrough hole and ground through hole disposed in the grid formation orin staggered formation just below the IC, which is a minimum unit, ispreferred to be in the stack condition and it is more preferable thatall the ground and power through holes just below the IC are formed inthe stack condition.

The ground through hole 36E and the power through hole 36P are disposedjust below the IC chip 90. By disposing them just below the IC chip 90,the distance between the IC 90 and the bump (external terminal) 96E, 96Pof the daughter board 94 or a capacitor (not shown) can be reduced.Thus, inductance can be decreased.

A distance (pitch) between the through holes 36E, 36P and 36S is set to80 to 600 μm and the signal through hole diameter 36S (outside diameter)is set to 50 to 400 μm. The distance (pitch) between the ground throughhole 36E and the power through hole 36P is set to 80-600 μm and thediameter (outside diameter) of the ground through hole 36E is set o 50to 400 μm and the diameter (outside diameter) of the power through hole36P is set to 50 to 400 μm (see FIG. 16). As the through holes 36E, 36P,36S, through conductive layers are formed in the core substrate 30 andtheir gaps are filled with insulating resin. Additionally, the inside ofthe through hole may be filled completely with conductive paste orplating. The signal through hole is preferred to be formed at otherportion than just below the IC. The portion just below IC is likely tobe affected by noise because the power through holes and ground throughholes are gathered in high density. Then, the pitch of the signalthrough hole is desired to be larger than the pitches of the powerthrough hole and the ground through hole. As a result, noise becomesunlikely to be loaded on a signal.

Here, the conductive layers 34P, 34E on the front surface side of thecore substrate 30 are formed in thickness of 5 to 40 μm, the innerconductive layers 16P, 16E are formed in the thickness of 5 to 250 μm,and the conductor circuit 58 on the interlayer resin insulating layer 50and the conductor circuit 158 on the interlayer resin insulating layer150 are formed in the thickness of 5 to 25 μm.

In the multi-layer printed wiring board of the first embodiment, byincreasing the thickness of the power layer (conductive layer) 34P andthe conductive layer 34 on the front surface side of the core substrate30 and the inner power layer (conductive layer) 16P, the conductivelayer 16E and the metallic plate 12 provided inside, the strength of thecore substrate is increased. As a result, even if the core substrateitself is thinned, warpage and stress generated can be relaxed by thesubstrate itself.

Further, by increasing the thickness of the conductive layers 34P, 34Eand the conductive layers 16P, 16E, the volume of the conductor itselfcan be increased. By increasing the volume, resistance of the conductorcan be reduced.

By using the conductive layers 34P, 16P as a power layer, the supplycapacity of power to the IC chip 90 can be improved. As a result, whenthe IC chip is mounted on the multi-layer printed wiring board, loopinductance from the IC chip to the substrate to the power supply can bereduced. Therefore, power shortage at an initial operation decreases, sothat the shortage of power becomes unlikely to occur and consequently,even if an IC chip in a high frequency region is mounted, no malfunctionor error is induced at the initial operation. Further, because theconductive layers 34E, 16E are used as the ground layer, noise does notoverlap a signal of the IC chip or supply of power, thereby preventingmalfunction or error. Because power accumulated in the capacitor can beused subsidiarily with the capacitor being mounted, the shortage ofpower becomes unlikely to occur.

FIG. 12 shows a modification of the first embodiment. According to themodification, the capacitor 98 is disposed just below the IC chip 90 anda conductive connection pin 99 is attached to the lower surface side. Ifthe capacitor 98 is disposed just below the IC chip 90, the effect ofmaking difficult the shortage of power is remarkable. The reason is thatjust below the IC chip, the wiring length on the multi-layer printedwiring board can be shortened.

FIG. 10(B) shows the arrangement of the through holes according to themodification of the first embodiment. FIG. 11(B) is an explanatorydiagram showing a portion II indicated with dotted line in FIG. 10(B) inenlargement. According to the modification of the first embodiment, thepower through holes 36P and the ground through holes 36E are disposed inthe staggered formation at adjacent positions. Such a configurationcancels out electromotive forces induced in the X direction and Ydirection.

As described with reference to FIG. 11(B), as for the through holes 36P,36E disposed in the staggered formation, the ground through holes GND1,GND2, GND3, GND4 are disposed around a single power through hole VCC. Atthis time, the ground through holes GND are preferred to be disposed atthe same distance to the power through hole VCC. Due to this structure,electromotive force induced in a single ground through hole GND (orpower through hole VCC) is cancelled out by one or more power throughholes VCC (or ground through hole GND). As a result, the mutualinductance of the through hole can be reduced and because an influenceof the induced electromotive force is received, malfunction or delaybecome unlikely to occur.

In Embodiment 1, the multilayer core substrate 30 has the thickconductor layers 16P and 16E on the inner layer and the thin conductorlayers 34P and 34E on the surface of the substrate 30, and the innerlayer conductor layers 16P and 16E and the surface layer conductorlayers 34P and 34E are employed as the power supply conductor layers andthe grand conductor layers, respectively. Namely, even if the thickconductor layers 16P and 16E are arranged on the inner layer side of thesubstrate 30, the resin layers covering the conductor layers are formed.Due to this, it is possible to cancel irregularities derived from theconductor layers and thereby flatten the surface of the multilayer coresubstrate 30. Therefore, even if the thin conductor layers 34P and 34Eare arranged on the surfaces of the multilayer core substrate 30 so asnot to generate waviness on the conductor layers 58 and 158 of therespective interlayer resin insulating layers 50 and 150, it is possibleto secure sufficient thickness as that of the conductor layers of thecore by the sum of the thicknesses of the conductor layers 16P and 16Eon the inner layer. Since no waviness occurs, no problem occurs to theimpedances of the conductor layers on the interlayer insulating layers.By employing the conductor layers 16P and 34P as the power supplyconductor layers and the conductor layers 16E and 34E as the grandconductor layers, it is possible to improve the electric characteristicsof the multilayer printed wiring board.

That is to say, the thicknesses of the conductor layers 16P and 16E onthe inner layer of the core substrate are set larger than those of theconductor layers 58 and 158 on the interlayer insulating layers 50 and150. By doing so, even if the thin conductor layers 34E and 34P arearranged on the surfaces of the multilayer core substrate 30, it ispossible to secure sufficient thickness as that of the conductor layersof the core by adding the thicknesses of the thick conductor layers 16Pand 16E on the inner layer. The thickness ratio of the conductor layerspreferably satisfies 1<(sum thickness of each inner conductor layer ofcore/conductor layer of insulating layer)≦40. More preferably, thethickness ratio satisfies 1.2≦(sum thickness of each inner conductorlayer of core/conductor layer of insulating layer)≦20.

The multilayer core substrate 30 is constituted so that the conductorlayers 16P and 16E as inner layer is formed on each surface of anelectrically isolated metallic plate 12 through a resin layer 14 and sothat the conductor layers 34P and 34E on the surface layer is formedoutside of the conductor layers 16P and 16E as the inner layer throughthe resin layer 18. By arranging the electrically insulated metallicplate 12 on the central portion of the substrate, it is possible tosecure sufficient mechanical strength. Further, by forming the conductorlayers 16P and 16E on the inner layer of the both surfaces of themetallic plate 12 through the resin layers 14, respectively and theconductor layers 34P and 34E on the surface layer on the outside of theconductor layers 16P and 16E as the inner layer on the both surfaces ofthe metallic plate 12 through the resin layers 18, respectively, it ispossible to impart symmetry to the both surfaces of the metallic plate12 and to prevent the occurrence of warps, waviness and the like in aheat cycle and the like.

Next, a method for manufacturing the multilayer printed wiring board 10shown in FIG. 8 will be described with reference to FIGS. 1 to 7.

(1) Formation of metallic layer

Openings 12 a are provided in an inner layer metallic layer (metallicplate) 12 having a thickness of 50 to 400 μm as shown in FIG. 1(A) topenetrate the front and rear surfaces of the layer 12 (FIG. 1(B)). Asthe material of the metallic layer, a material containing a mixture ofcopper, nickel, zinc, aluminum, iron and the like can be used. Theopenings 12 a are formed by punching, etching, drilling, a laser or thelike. Depending on cases, metallic films 13 may be coated on the entiresurfaces of the metallic layer 12 having the openings 12 a formedtherein by electroplating, electroless plating, substitutional platingor sputtering (FIG. 1(C)). The metallic plate 12 may comprise a singlelayer or a plurality of layers of two or more layers. In addition, themetallic films 13 preferably have curves. The curves can eliminatepoints at which stresses are concentrated and make it more difficult tocause defects such as cracks and the like around the points.

(2) Formation of insulating layers on inner layer

Insulating resin is used to cover the entire surfaces of the metalliclayer 12 and fill up the openings 12 a. For example, the metallic plate12 is put between resin films in a B stage state of a thickness of about30 to 200 μm, the resin films are thermally pressed and hardened,whereby insulating rein layers 14 can be formed (FIG. 1(D)). Dependingon cases, the insulating rein layers 14 may be formed out of films afterapplying resin, applying resin and press-fitting the resin films orapplying the resin only to the opening portions.

As the material of the insulating resin layers 14, a prepreg having acore material such as glass cloth impregnated with thermosetting resinsuch as polyimide resin, epoxy resin, phenol resin or BT resin ispreferable. The other resin may be used.

(3) Bonding of metallic foils

Metallic layers 16α on the inner layer are formed on the both surfacesof the metallic layer 12 covered with the resin layers 14, respectively(FIG. 1(E)). By way of example, metallic foils having a thickness of 12to 275 μm are built on the both surfaces thereof. As an alternative tothe method for forming the metallic foils, a one-sided copper-cladlaminate is built up on each surface of the metallic layer 12. Thelaminate can be formed on the metallic foils by plating or the like.

(4) Formation of circuits of metallic layer on the inner layer

Two or more layers may be formed. The metallic layer may be formed bythe additive method.

Through a denting method, etching steps and the like, conductor layers16P and 16E on the inner layer are formed from the inner layer metalliclayer 16 a (FIG. 1(F)). The inner layer conductor layers are formed tohave thicknesses of 10 to 250 μm.

(5) Formation of insulating layers as outer layers

Insulating resin is used to cover the entire surfaces of the inner layerconductor layers 16P and 16E and fill up the gaps between the circuitsof outer layer metal. By way of example, outer layer insulating resinlayers 18 are formed by putting the metallic plate between resin filmsin a B stage state of a thickness of about 30 to 200 μm, thermallypress-fitting and hardening the resin films (FIG. 2(A)). Depending oncases, the outer layer insulating resin layers 18 may be formed out offilms after applying resin, applying resin and press-fitting the resinfilms or applying the resin only to the opening portions. By applyingpressure, it is possible to flatten the surfaces of the layers 18.

(6) Bonding of outermost layer metallic foils

Outermost metallic layers 34 a are formed on the both surfaces of thesubstrate covered with the outer layer insulating resin layers 18 (FIG.2(B)). By way of example, metallic foils having a thickness of 12 to 275μm are built up on the both surfaces of the substrate. As an alternativeto the method for forming the metallic foils, one-sided copper-cladlaminates are built up. Two or more layers of the laminates may beformed on the metallic foils. The metallic layers may be formed by theadditive method.

(7) Formation of through holes

Pass-through holes 36 a for through holes having opening diameter of 50to 500 μm are formed to penetrate the front and rear surfaces of thesubstrate (FIG. 2(C)). As a formation method, the holes are formed bydrilling, a laser or a combination of drilling and the laser. (The holesare opened in the outermost insulating layers by the laser, and then maybe penetrated through the substrate by drilling while using the holesopened by the laser as target marks.) The forms of the holes arepreferably those having linear sidewalls. Depending on cases, the holesmay be tapered. The distance (pitch) between the through holes is 60 to600 μm.

To secure the conductive properties of the through holes, it ispreferable to form plated films 22 in the respective pass-through holes36 a for the through holes and roughen the surfaces of the plated films22 (FIG. 2(D)), and then to fill the holes with resin filler 23 (FIG.2(E)). As the resin filler, either an electrically insulated resinmaterial (e.g., a resin material containing a resin component, hardeningagent, particles and the like) or a conductive material holdingelectrical connection by metallic particles (e.g., a conductive materialcontaining metallic particles such as gold or copper particles, a resinmaterial, hardening agent and the like) can be used.

As plating, electroplating, electroless plating, panel plating(electroless plating and electroplating) or the like may be performed.The plated films 22 are formed by plating metals containing copper,nickel, cobalt, phosphorus or the like. The thicknesses of the platedmetals are preferably 5 to 30 μm.

The resin filler 23 filled in the pass-through holes 36 a for thethrough holes is preferably made of an insulating material comprising aresin material, hardening agent, particles and the like. As theparticles, inorganic particles such as silica or alumina particles canbe used solely, metallic particles such as gold, silver or copperparticles can be used solely, resin particles can be used solely or theinorganic particles, the metallic particles and the resin particles canbe mixed together. The particles equal in particle size from 0.1 to 5 μmor different in particle size from 0.1 to 5 μm can be mixed. As theresin material, thermosetting resin such as epoxy resin (e.g., bisphenoltype epoxy resin or novolac type epoxy resin and the like) or phenolresin, ultraviolet setting resin having a photosensitive property,thermoplastic resin or the like may be used solely or mixed together. Asthe hardening agent, imidazole based hardening agent, amine basedhardening agent or the like can be used. Alternatively, hardening agentcontaining hardening stabilizer, reaction stabilizer, particles and thelike may be used. In the latter case, the resin filler is replaced byconductive paste made of a conductive material comprising metallicparticles, a resin component, hardening agent and the like. Depending oncases, metallic films having a conductive property may be formed on thesurface layers of an insulating material such as solder or insulatingresin. It is also possible to fill the pass-through holes 36 a forthrough holes with plated members. Since the conductive paste ishardened and contracted, depressed portions are sometimes formed on thesurface layers.

The formed through holes are grand through hole 36E and power throughholes 36P, as mentioned with referring to FIG. 11(A), are placed as thelattice arrangement.

(8) Formation of outermost layer conductor circuits

Cover plated members 25 may be formed right on the through holes 36S,36E, 36P by coating plated films on the entire surfaces of the substrate(FIG. 3(A)). Thereafter, outer layer conductor circuits 34, 34P and 34Eare formed through the denting method, etching steps and the like (FIG.3(B)). As a result, the multilayer core substrate 30 is completed.

At this time, although not shown in the drawings, the electricalconnection of the outer conductor circuits to inner conductor layers16P, 16E and the like of the multilayer core substrate may beestablished by via holes, blind through holes or blind via holes.

(9) The multilayer core substrate 30 on which the conductor circuits 34have been formed thereon is subjected to a blackening treatment and areduction treatment, thereby forming roughened surfaces 34β on theentire surfaces of the conductor circuits 34 and the conductor layers34P and 34E (FIG. 3(C)).

(10) Layers of the resin filler 40 are formed on the conductor circuitunformed portions of the multilayer core substrate 30 (FIG. 4(A)).

(11) The one surface of the substrate which has been subjected to theabove treatments is polished by belt sander polishing or the like so asnot to leave the resin filler 40 on the outer edges of the conductorlayers 34P and 34E, and then the entire surfaces of the conductor layers34P and 34E (including the land surfaces of the through holes) arefurther polished by buffing or the like so as to eliminate scratchescaused by the former polishing. A series of polishing operations aresimilarly conducted to the other surface of the substrate. Next, theresin filler 40 is hardened by heat treatments at 100° C. for 1 hour and150° C. for 1 hour (FIG. 4(B)).

The resin filler may not be filled between the conductor circuits. Inthat case, using resin layers such as interlayer insulating layers, theinsulating layers are formed and the portions between the conductorcircuits are filled up.

(12) Etchant is sprayed onto the both surfaces of the multilayer coresubstrate 30 and the surfaces of the conductor circuits 34 and theconductor layers 34P and 34E and the land surfaces and inner walls ofthe through holes 36S, 36E, 36P are subjected to etching or the like,thereby forming roughened surfaces 36β on the entire surfaces of theconductor circuits (FIG. 4(C)).

(13) Resin films 50γ for interlayer resin insulating layers are mountedon the both surface of the multilayer core substrate 30, respectively,temporarily press-fitted and cut, and then bonded onto the substrateusing the vacuum laminator, thereby forming interlayer resin insulatinglayers (FIG. 5(A)).

(14) Thereafter, through a mask having pass-through holes having athickness of 1.2 mm formed therein, openings 50 a for via holes areformed to have a diameter of 80 μm in the interlayer resin insulatinglayers 50 by a CO2 gas laser having wavelength of 10.4 μm underconditions of a beam diameter of 4.0 mm, a top hat mode, a pulse widthof 7.9 microseconds, the pass-through hole diameter of the mask of 1.0mm and one shot (FIG. 5(B)).

(15) The multilayer core substrate 30 is immersed in a solutioncontaining 60 g/l of permanganic acid at 80° C. for 10 minutes to formroughened surfaces 50 a on the surfaces of the interlayer resininsulating layers 50 including the inner walls of the via hole openings50 a (FIG. 4(C)). The roughened surfaces are formed to have a thicknessbetween 0.1 to 5 μm.

(16) Next, the multilayer core substrate 30 which has been subjected tothe above-stated treatments is immersed in neutralizer (manufactured byShipley Corporation) and then washed. Further, a palladium catalyst isadded to the surfaces of the roughened substrate (a roughening depth of3 μm), thereby attaching catalyst nuclei to the surfaces of theinterlayer resin insulating layers and the inner wall surfaces of thevia hole openings.

(17) The substrate to which the catalyst is attached is immersed in anelectroless copper plating aqueous solution and electroless copperplated films having a thickness of 0.6 to 3.0 μm are formed on theentire roughened surfaces, thereby obtaining the substrate havingelectroless copper plated films 52 formed on the surfaces of theinterlayer resin insulating layers 50 including the inner walls of thevia hole openings 50 a (FIG. 4(D)).

(18) Commercially available dry films are bonded to the substrate onwhich electroless copper plated films 52 are formed, a mask is put onthe substrate, the substrate is developed and plating resists 54 arethereby provided (FIG. 6(A)). The plating resists having a thickness of10 to 30 μm are used.

(19) Next, the multilayer core substrate 30 is electroplated, therebyforming electroplated copper films 56 having a thickness of 10 to 20 μmare formed on portions in which the plating resists 54 are not formed,respectively (FIG. 6(B)).

(20) After peeling off the plating resists with 5% KOH, the electrolessplated films under the plating resist are etched, molten and removedwith a solution mixture of sulfuric acid and hydrogen peroxide, thusforming independent conductor circuits 58 and via holes (filled-via) 60(FIG. 6(C)).

(21) Next, the same treatment as that of (12) is conducted to formroughened surfaces 58 a and 60 a on the surfaces of the conductorcircuits 58 and via holes 60. The upper conductor circuits 58 are formedto have a thickness of 10 to 25 μm. In this example, the upper conductorcircuits 58 have a thickness of 15 μm (FIG. 6(D)).

(22) The steps (14) to (21) stated above are repeated, thereby formingfurther upper layer conductor circuits 158, via holes 160, interlayerresin insulating layers 150, and a multilayer wiring board is obtained(FIG. 7(A)).

(23) Next, after the above-stated solder resist composition 70 is coatedon each surface of the multilayer wiring board by a thickness of 12 to30 μm, and dried under conditions of 70° C. for 20 minutes and 70° C.for 30 minutes (FIG. 7(B)), a photomask on which a pattern of solderresist opening portions are drawn and which has a thickness of 5 mm, isfixedly attached to each solder resist layer 70, exposed withultraviolet rays of 1000 mJ/cm², and developed with a DMTG solution,thereby forming opening portions 71 having a diameter of 200 μm (FIG.7(C)). Further, heat treatments are conducted at 80° C. for 1 hour, at100° C. for 1 hour, at 120° C. for 1 hour, and at 150° C. for 3 hours,respectively, to harden the solder resist layers, thus forming solderresist pattern layers each having opening 71 and a thickness of 10 to 25μm.

(24) Next, the substrate on which the solder resist layers 70 are formedis immersed in an electroless nickel plating solution, thereby formingnickel plated layers 72 having a thickness of 5 μm on the openingportions 71, respectively. Furthermore, the substrate is immersed in anelectroless gold plating solution, thereby forming gold plated layers 74having a thickness of 0.03 μm on the respective nickel plated layers 72(FIG. 7(D)). Alternatively, a single tin or noble metal (gold, silver,palladium, platinum or the like) layer may be formed in stead of thenickel-gold layers.

(25) Thereafter, tin-lead containing solder paste is printed on eachopening 71 of the solder resist layer 70 on one surface of the substrateon which surface the IC chip is mounted, tin-antimony containing solderpaste is further printed on each opening on the other surface of thesubstrate, and external terminals are formed by conducting reflow at200° C., thereby manufacturing a multilayer printed wiring boardincluding solder bumps 76U, 76D (FIG. 8).

Second Embodiment 3-Layer Multi-Layer Core Substrate

The multi-layer printed wiring board according to the second embodimentwill be described with reference to FIG. 13.

According to the first embodiment described with reference to FIG. 8,the core substrate is composed of four layers (ground layers 16E, 34E:2, power layers 16P, 34P: 2). Contrary to this, according to the secondembodiment, as shown in FIG. 13, the multi-layer core substrate 30 iscomposed of three layers (ground layers 34E, 34E: 2, power layer 15P:1).

In the multi-layer printed wiring board 10 according to the secondembodiment, as shown in FIG. 13, the conductor circuit 34 and the groundconductive layer 34E are formed on each of the front surface and therear surface of the multi-layer core substrate 30 and the powerconductive layer 15P is formed inside the core substrate 30. The groundconductive layer 34E is formed as a ground plain layer and the powerconductive layer 15P is formed as a power plain layer. The groundthrough hole 36E is connected to the ground conductive layers 34E on theboth surfaces of the core substrate and the power through hole 36P isconnected to the power conductive layer 15P in the center of the coresubstrate. A signal is connected to the both surfaces of the multi-layercore substrate 30 via the signal through hole 36S. On the groundconductive layer 34E are disposed the interlayer resin insulating layer50 in which the via hole 60 and the conductor circuit 58 are formed andthe interlayer resin insulating layer 150 in which the via hole 160 andthe conductor circuit 158 are formed. The solder resist layer 70 isformed above the via hole 160 and the conductor circuit 159 and thebumps 76U, 76D are formed in the via hole 160 and the conductor circuit158 via the opening portion 71 of the solder resist layer 70.

According to the second embodiment also, like the first embodimentdescribed with reference to FIGS. 10(A), 10(B), the power through holes36P and the ground through holes 36E are disposed in the grid formationor in the staggered formation so as to reduce mutual inductance.

The conductor circuit 34 and the conductive layer 34E are formed on thecore substrate 30 and the conductive layer 15P is formed inside the coresubstrate. On the other hand, the conductor circuit 58 is formed on theinterlayer resin insulating layer 50 and the conductor circuit 158 isformed on the interlayer resin insulating layer 150. The conductivelayer 34E on the core substrate is formed in the thickness of 1 to 250μm and the conductive layer 15P taking as a power layer formed insidethe core substrate is formed in the thickness of 1 to 250 μm. Thethickness of the conductive layer in this case is total values of thethicknesses of the power layers in the core substrate. It means thatthis is sum of both the conductive layer 15P as the inner layer and theconductive layer 34E as the front surface layer. This does not mean sumof layers taking as a signal line. By summing up the thicknesses of thethree layers, the three conductive layers 34E, 15P, the same effect asthe first embodiment is obtained. The thickness of the power layer mayexceed the above-described range.

Modification of the Second Embodiment

FIG. 14 shows a sectional view of the multi-layer printed wiring boardaccording to the modification of the second embodiment. Althoughaccording to the second embodiment described with reference to FIG. 13,the multi-layer core substrate 30 is composed of three layers (groundlayers 34E, 34E: 2, power layer 15P: 1), according to the modificationof the second embodiment, the multi-layer core substrate 30 is composedof three layers (ground layer 15E: 1, power layers 34P, 34P: 2).

As shown in FIG. 14, in the multi-layer printed wiring board 10according to the second embodiment, the conductor circuit 34 and thepower conductive layer 34P are formed on the front surface and rearsurface sides of the multi-layer core substrate 30 while the groundconductive layer 15E is formed inside the core substrate 30. The groundconductive layer 15E is formed as a ground plain layer and the powerconductive layers 34P, 34P are formed as a power plain layer. The groundthrough hole 36E is connected to the ground conductive layers 15E, 15Ein the center of the core substrate and the power through hole 36P isconnected to the power conductive layers 34P, 34P on both sides of thecore substrate. A signal is connected to both faces of the multi-layercore substrate 30 via the signal through hole 36S. Above the powerconductive layer 34P are disposed the interlayer resin insulating layer50 in which the via hole 60 and the conductive circuit 58 are formed andthe interlayer resin insulating layer 150 in which the via hole 160 andthe conductor circuit 158 are formed.

According to the modification of the second embodiment also, like thefirst embodiment described above with reference to FIG. 10 (A), (B), thepower through hole 36P and the ground through hole 36E are disposed inthe grid formation or in the staggered formation so as to reduce mutualinductance. According to the modification of the second embodiment also,the three conductive layers 34P, 34P, 15E in the multi-layer coresubstrate 30 and the conductor circuits 58, 158 in the interlayer resininsulating layers 50, 150 are formed in the same thickness as the secondembodiment so as to secure the same effect.

Third Embodiment Glass Epoxy Resin Substrate

Although in the first and second embodiments, the multi-layer coresubstrate 30 is employed, according to the third embodiment, a singlecore substrate 30 is used as shown in FIG. 15 and the conductive layerson both sides of the core substrate are formed as the power layer andground layer. That is, the ground layer 34E is formed on top of the coresubstrate 30 and the power layer 34P is formed on the bottom thereof.The front surface and rear surface of the core substrate 30 areconnected via the power through hole 36P, the ground through hole 36Eand the signal through hole 36S. Above the conductive layers 34P, 34Eare disposed the interlayer resin insulating layer 50 in which the viahole 60 and the conductive layer 58 are formed and the interlayer resininsulating layer 150 in which the via hole 160 and the conductor circuit158 are formed.

According to the third embodiment also, like the first embodimentdescribed with reference to FIG. 10(A), (B), the power through hole 36Pand the ground through hole 36E are disposed in the grid formation or inthe staggered formation so as to reduce mutual inductance.

The conductive layers 34P, 34E on the core substrate 30 is formed in thethickness of 1 to 250 μm, and the conductor circuit 58 on the interlayerresin insulating layer 50 and the conductor circuit 158 on theinterlayer resin insulating layer 150 are formed in the thickness of 5to 25 μm (preferably, 10 to 20 μm).

In the multi-layer printed wiring board of the third embodiment, thethicker the power layer (conductive layer) 34P and the conductive layer34E of the core substrate 30, the stronger the core substrate is. Thus,even if the thickness of the core substrate itself is decreased, warpageand stress generated can be relaxed by the substrate itself. Further, bythickening the conductive layers 34P, 34E, the volume of the conductoritself can be increased. By increasing the volume, resistance of theconductor can be reduced.

Further, by using the conductive layer 34P as a power layer, supplycapacity of power to the IC chip can be improved. Thus, when the IC chipis mounted on the multi-layer printed wiring board, loop inductance fromthe IC chip to the substrate to the power supply can be reduced. As aresult, shortage of power at an initial operation decreases, so that theshortage of power becomes unlikely to occur. For the reason, even if anIC chip in a high frequency region is mounted, the malfuction or errorin the initial startup is never induced. Further, by using theconductive layer 34E as a ground layer, overlapping of noise on signalsof the IC chip and supply of power is eliminated thereby preventing themalfunction or error.

Comparative Example

The comparative example is almost the same as the first embodimentexcept that the ground through hole and the power through hole areformed at a position in which they do not adjoin each other. That is,the ground through holes and the power through holes were formed atrandom and the shortest distance (through hole pitch) between the groundthrough hole and the power through hole were set in eight kinds from 80to 650 μm as shown in FIG. 16. The same Figure shows the through holediameter. These are disposed at random as described in FIG. 16.

A first reference example is almost the same as the first embodimentexcept that the distance between the ground through hole and the powerthrough hole was over 600 μm. As an example thereof, the distance wasset to 650 μm.

As a second reference example, almost the same piece as the thirdembodiment was produced except that the distance between the groundthrough hole and the power through hole was over 600 μm. As an examplethereof, a piece was produced in a condition in which the distance wasset to 650 μm. The loop inductance became the same as the firstreference example.

As a third reference example, almost the same piece as the firstembodiment was produced except that the thickness of the core substratewas decreased for achieving multiple layers and the diameters of theground through hole and power through hole were set to 25 μm while thedistance between the ground through hole and the power through hole wasset to less than 60 μm. As an example thereof, a piece was produced in acondition in which the distance was set to 50 μm. The sum of thethicknesses of respective conductive layers of the multi-layer coresubstrate is the same as the first embodiment.

FIG. 16 shows a result of measurement of each loop inductance in casewhere the through holes in the multi-layer printed wiring board of thefirst embodiment are disposed in the grid formation (thick copper), acase where the through holes are disposed in the staggered formation asa modification of the first embodiment (thick copper) and a case wherethe through holes are disposed at random with the sum of the thicknessesof respective conductive layers in the multi-layer core substrate of thefirst embodiment set to the same as the thickness of the conductivelayer on the interlayer insulating layer, as the fourth referenceexample and comparative example. The value of the loop inductance is avalue per 2.5 mm².

The grid formation (thick copper) or the staggered formation (thickcopper) [a structure in which the ground through hole and the powerthrough hole adjoin each other] can reduce the loop inductance more thanthe random formation (a structure in which the ground through hole andthe power through hole do not adjoin) even if the through hole pitch ischanged. As a consequence, delay is suppressed, so that power supplytime to a transistor of the IC is reduced. Even if an IC exceeding 3 GHzis mounted, the transistor is not short of power.

The grid formation reduces the loop inductance more than the staggeredformation regardless of the through hole pitch. Thus, it can be said tobe superior in terms of electric characteristic. It is evident from FIG.16 that the loop inductance is lower if the ground through holes 36E andthe power through holes 36P are disposed diagonally.

If comparing the grid formation (thick copper) of FIG. 16 with thefourth reference example, in the case of the same grid formation, a casewhere the sum of the thicknesses of the respective conductive layers inthe multi-layer core substrate was larger provided a more excellentvalue under any through hole pitch. This reason is estimated to be thatthe through hole and the side wall of the conductive layer cancels outinductances together.

By changing the through hole pitch, the loop inductance was calculatedby simulation. FIG. 17(B) indicates its result. The value of the loopinductance here is a value per 2.5 mm².

Further, reliability test was carried out on a substrate in the gridformation and the staggered formation at each through hole pitch underhigh-temperature, high-humidity condition (carried out at 85° C., 85 wt% in humidity for 500 hours). FIG. 17(A) shows whether or not there isany crack in the insulating layer of the through hole and a resistancemeasurement result in conductivity test. As evident from FIG. 17(B),although loop inductance decreased if the through hole pitch wasreduced, if it is less than 60 μm, conversely the loop inductance rose.The reason is estimated to be that the loop inductance rose because thethrough hole pitch at the same potential narrowed or that selfinductance increased because the through hole diameter was reduced.

If the loop inductance is large, supply of power to the transistor ofthe IC is delayed. If the driving frequency of the IC is accelerated,time taken for the transistor to make a next ON from a ON shortens. Ifthe voltage of the transistor is insufficient, the transistor does notoperate.

If the loop inductance drops to 75 pH or less, the voltage is restoredto a voltage which operates the transistor of the IC properly until itturns ON next even if with the IC chip whose frequency is 3 GHz loadedand simultaneous switching is repeated, thereby hardly causingmalfunction. In this case, as evident from FIG. 16, the loop inductancenever drops to 75 pH or less under the random formation. Malfunction islikely to occur under the random formation. As a result of mounting anIC whose frequency was 1, 3, 5 GHz on a random formation printed wiringboard and repeating the simultaneous switching 10,000 times, the ICshaving 3 GHz, 5 GHz malfunctioned although the IC having 1 GHz operatedproperly.

In case of the grid formation, the through hole pitch is desired to be600 μm or less. This range can reduce the loop inductance to a specificlevel (75 pH or less). Further, if the through hole pitch is between 80and 600 μm, the loop inductance rests within that given loop inductanceregion and at the same time, reliability can be secured.

In case of the staggered formation, the through hole pitch is desired tobe 550 μm or less. Such a range can reduce the loop inductance to thespecific level (75 pH or less). Further, if the through hole pitch isbetween 80 and 550 μm, the loop inductance rests within that given loopinductance and at the same time, reliability can be secured.

If the loop inductance drops to less than 60 pH, even if with an IC chipwhose frequency is 5 GHz loaded and simultaneous switching is repeated,malfunction hardly occurs. In this case, as evident from FIG. 16, incase of the grid formation, the through hole pitch is desired to bebetween 80 and 550 μm. Such a range can reduce the loop inductance levelto less than 60 pH. Then, if the through hole pitch is between 80 and550 μm, the loop inductance rests within that given loop inductanceregion and at the same time, reliability can be secured.

In case of the staggered formation, as evident from FIG. 16, the throughhole pitch is desired to be between 80 and 450 μm. Such a range canreduce the through inductance level to less than 60 pH. Then, if thethrough hole pitch is between 80 and 450 μm, the loop inductance restswithin that given loop inductance region and at the same time,reliability can be secured.

Further, if the loop inductance drops to 55 pH or less, malfunctionhardly occurs even if the simultaneous switching is repeated regardlessof the frequency of the IC chip. According to the result of FIG. 16, ifin the case of the grid formation, the through hole pitch is between 80and 450 μm, such a result is generated. Then, if the through hole pitchis between 80 and 450 μm, the loop inductance rests within that givenloop inductance and at the same time, reliability can be secured. On theother hand, according to the result of simulation, such a result isprovided if the through hole pitch is between 60 and 450 μm.

FIG. 19 shows a result of measuring the amount of voltage drop when aprinted wiring board was manufactured by changing the sum of thethicknesses of respective conductive layers in the multi-layer coresubstrate and with the IC chip whose frequency was 3.1 GHz loaded, theprinted wiring board was started by supplying the same amount of power.Because the voltage of the IC could not be measured directly through theIC, the printed wiring board was provided with a measuring circuit.(ratio of sum of the thicknesses of conductive layers in the multi-layercore substrate/thickness of the conductive layer on interlayerinsulating layer) is set on the abscissa axis and a maximum voltage drop(V) is set on the ordinate axis.

If when the voltage of power is 1.0 V, it is within deflection allowancerange ±10%, it comes that the behavior of the voltage is stable, therebynever inducing the malfunction of the IC chip. That is, if the amount ofvoltage drop is 0.1 V or less, it comes that any malfunction of the ICchip by voltage drop is never induced. For the reason, the ratio of (sumof thicknesses of conductive layers in the multi-layer coresubstrate/thickness of conductive layer on interlayer insulating layer)exceeds 1.2. Further, if 1.2≦(sum of thicknesses of conductive layers inthe multi-layer core substrate/thickness of conductive layer oninterlayer insulating layer)≦40, the numeric value tends to decrease andthus, its effect is easy to obtain. On the other hand, if 40<(sum ofthicknesses of conductive layers in the multi-layer coresubstrate/thickness of conductive layer on interlayer insulating layer),the amount of voltage drop is rising. Because current likely flows onthe front surface, if the conductive layer is thick, it is estimatedthat the voltage drop increases because its moving distance in thethickness direction lengthens.

Further, if 5.0<(sum of thicknesses of conductive layers in themulti-layer core substrate/thickness of conductive layer on interlayerinsulating layer)≦40, the amount of voltage drop is almost the same,meaning that the voltage is stable. That is, it can be said that thisrange is most desirable ratio range.

If the thickness of the conductor is too small, peeling occurs in a viahole connection portion, whereby the reliability dropping. However, ifthe ratio of the sum of thicknesses of the conductive layers in themulti-layer core substrate/thickness of the conductive layer on theinterlayer insulating layer exceeds 1.2, the reliability is raised. Onthe other hand, if the ratio of the sum of thicknesses of the conductivelayers in the multi-layer core substrate/thickness of the conductivelayer on the interlayer insulating layer exceeds 40, the reliabilitydrops because of fault in the conductor circuit on the upper layer (forexample, adhesion drops due to generation of stress in the conductorcircuit on the upper side or swelling).

According to the present invention, the ground through holes and thepower through holes are disposed in the grid formation or in thestaggered formation and because the ground through hole and the powerthrough hole adjoin each other so that the directions of electromotiveforces generated in each are opposite, the induced electromotive forcesin the X direction and Y direction cancel out each other. Thus, thespeed of supply of power to the transistor of the IC is accelerated. Forthe reason, malfunction is eliminated. If the printed wiring board ofthe present invention is used, even if the transistor of the IC repeatsON/OFF rapidly, the potential of the transistor never drops.

Because the sum of the thicknesses of the conductive layers in themulti-layer core substrate is larger than the thickness of theconductive layer on the interlayer insulating layer so that thethickness of the conductive layer in the inner layer is thickened,induced electromotive forces are cancelled out between the side wall ofthe ground conductive layer in the inner layer (or side wall of thepower conductive layer in the inner layer) and the power through hole(or ground through hole). Therefore, the loop inductance drops more thana printed wiring board using the same multi-layer core substrate as thesum of the thicknesses of the conductive layers on both sided coresubstrate or the interlayer insulating layer and the thickness of therespective conductive layers in the multi-layer core substrate. Thus, ifa high frequency IC chip, particularly, an IC chip in a high frequencyregion of 3 GHz or more is mounted, the voltage of the transistor in theIC is always stabilized and as a consequence, no malfunction or erroroccurs so as to improve the electric characteristics and reliability.

1-17. (canceled)
 18. A multi-layer printed wiring board comprising: acore substrate comprising: a resin structure having a planar top resinsurface and a planar bottom resin surface which is opposite to theplanar top resin surface, a plurality of conductive layers including atop conductive layer formed directly on the planar top resin surface,and a bottom conductive layer formed directly on the planar bottom resinsurface, said top and bottom conductive layers each being a groundconductive layer, each being a power conductive layer, or being a groundconductive layer and power conductive layer respectively, and aplurality of through holes in the core substrate and disposed so that aground through hole and a power through hole are adjacent each other,wherein a distance between the ground through hole and the power throughhole is in a range of 60 to 550 μm; an interlayer insulating layerformed on the core substrate; a conductive layer formed on theinterlayer insulating layer; and a plurality of via holes provided inthe insulating layer and configured to provide electrical connectionbetween the conductive layer and through holes.
 19. The multi-layerprinted wiring board according to claim 18, wherein the ground throughhole in the core substrate including two or more ground through holesand the power through hole including two or more power through holes,such that the ground through holes and the power through holes aredisposed in a grid formation or in a staggered formation at adjacentpositions.
 20. The multi-layer printed wiring board according to claim18, wherein the diameter of the ground through hole is 50 to 500 μm andthe diameter of the power through hole is 50 to 500 μm.
 21. Themulti-layer printed wiring board according to claim 18, wherein at leastone through hole of the ground through holes and the power through holescomprises two or more through holes in a stack structure through alllayers of the multi-layer printed wiring board up to an outermost layer.22. The multi-layer printed wiring board according to claim 18, whereinthe ground through hole and the power through hole are disposed justbelow an IC chip.
 23. The multi-layer printed wiring board according toclaim 18, wherein a thickness of each of the top and bottom conductivelayers on the core substrate is larger than a thickness of theconductive layer on the interlayer insulating layer.
 24. The multi-layerprinted wiring board according to claim 18, wherein assuming that thethickness of the conductive layers on the core substrate is α1 and athickness of the conductive layer on the interlayer insulating layer isα2, α2<α1≦40α2.
 25. The multi-layer printed wiring board according toclaim 24, wherein the α1 is in a relation of 1.2α2≦α1≦40α2.
 26. Themulti-layer printed wiring board according to claim 23, wherein each ofthe plurality of conductive layers of the core substrate is a conductivelayer for power or conductive layer for grounding.
 27. The multi-layerprinted wiring board according to claim 18, wherein a capacitor ismounted on the surface thereof.
 28. The multi-layer printed wiring boardaccording to claim 18, wherein the core substrate is a multi-layer coresubstrate with said plurality of conductive layers comprising three ormore conductive layers including a thick conductive layer as an innerlayer of the multi-layer core substrate, and said top and bottomconductive layers, wherein each conductive layer of the core substrateis a conductive layer for power or a conductive layer for grounding. 29.The multi-layer printed wiring board according to claim 18, wherein thecore substrate is a multi-layer core substrate composed of threeconductive layers including a thick conductive layer as an inner layerof the multi-core substrate, and said top and bottom conductive layers,wherein the inner conductive layer of the core substrate is a conductivelayer for power or conductive layer for grounding, and at least one ofthe top or bottom conductive layer includes a signal line.
 30. Themulti-layer printed wiring board according to claim 28, wherein athickness of the conductive layer of the inner layer of the coresubstrate is larger than a thickness of the conductive layer on theinterlayer insulating layer.
 31. The multi-layer printed wiring boardaccording to claim 29, wherein the conductive layer in the inner layerof the core substrate comprises two or more layers.
 32. The multi-layerprinted wiring board according to claim 28, wherein the core substrateis so constructed that the thick conductive layer is disposed as theinner layer and a thin conductive layer is formed as one of the top andbottom conductive layers.